PCIe-over-Cable and CvP Evaluation System

Why use PCIe-over-Cable

System setup requirements

Often, PCIe peripherals are placed in a PC enclosure. In some cases, where a lot of (flexible) connections are to be made to (for instance) Lab equipment, the PCIe device does not fit inside a PC.

In those cases, the PCIe device sits on a bench, and is connected to a PC via a PCIe-over-Cable.

This is where PCIe-over-Cable is used to connect the device to the PC.

Protocol benefits

There are several benefits of PCIe over other interfaces:

  • Low cost
  • Low power
  • High bandwidth
  • Software transparency
  • Low latency

How to use PCIe-over-Cable and FPGAs

Modern FPGAs often feature high-speed serial interfaces, which can be configured to implement various high-speed interfaces. PCIe is one of them.

The challenge in using PCIe-over-Cable lies in the fact that PCIe expects all connected devices to be ready for link-training within approximately 100ms after power up. Most FPGAs take a lot longer to configure after power up, which prevents the PCIe-root to ignore it.

Configuration-via-Protocol (CvP) allows an FPGA to quickly load a minimal configuration, performing the minimal PCIe tasks, allowing the PCIe root to see the device, and perform link training. When the OS has started, it can load the driver for the device and finish configuring the device.

What the Evaluation system provides

  • Board
    • PCIe x1 cable connector
    • Powered from its PCIe-over-Cable interface connector or header
    • 8 status leds
    • 32 Parallel IOs (3v3), connected to 0.1" header area
    • DCDC Power converters
    • 100MHz oscillator
    • Serial Flash for storage of the periphery image of the CvP configuration
  • Qsys design, implementing the PCIe Hard-ip, DMA controller, internal RAM (to act as DMA source)
  • Linux driver to perform PCIe benchmarks using DMA, control the leds, readout PCIe configuration space, readout on-chip memory and perform CvP
  • Linux example driver (from Altera), which performs the CvP and loads the core-configuration into the FPGA.

More Information

For more information, see the contact page on this website.